Many electrical, electronic, and computer-related applications, such as, for example, modern digital signal processing, rely heavily on mathematical calculations, and the multiplication operation represents a significant portion of those calculations. In many instances, a digital multiplier is universally utilized as an arithmetic unit in microprocessors, digital signal processors (DSPs), emerging media processors, and the like. These multipliers are used to perform various functions, including, but not limited to, address generation, fast Fourier transformations (FFTs), discrete cosine transformations (DCTs), etc. Consequently, multipliers play a critical role in processing multimedia and other data.
With the ever increasing amounts data that must be processed, it is necessary that the multiplication operation be as fast as possible. Unfortunately, however, multiplication is an inherently slow operation, particularly in the context of digital signal processing, wherein such multiplication operations are required to be implemented by instructions supported by modern DSP cores and other arithmetic logic units (ALUs). In contrast to simple addition, multiplication requires that each digit of the multiplicand be multiplied by each digit of the multiplier to arrive at the partial products. These partial products must be subsequently added together to generate a final result. Moreover, many mathematical operations use a negated result of the multiplication.
Implementing a negative multiplication function in an ALU (e.g., a DSP core) generally requires negation of the multiplication result in two's complement number representation. In two's complement number representation, a negation involves performing a bitwise NOT operation followed by an increment of the result by one. The increment by one operation can sometimes be incorporated into other addition logic, which makes the control logic used to implement the process more complex. In other cases, the increment by one operation may require separate dedicated circuitry, such as, for example, incrementer logic, which is relatively large in terms of integrated circuit (IC) area. In either case, the required additional circuitry increases IC area utilization and power consumption, and is therefore undesirable.